PART |
Description |
Maker |
IS61NP25632 IS61NP25636 IS61NP51218 IS61NP25632-5T |
256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 512K X 18 ZBT SRAM, 4.2 ns, PBGA119 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 512K X 18 ZBT SRAM, 5 ns, PBGA119 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K X 32 ZBT SRAM, 4.2 ns, PBGA119 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K X 32 ZBT SRAM, 5 ns, PBGA119 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K X 32 ZBT SRAM, 5 ns, PQFP100 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K X 36 ZBT SRAM, 4.2 ns, PQFP100 Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 256K X 36 ZBT SRAM, 5 ns, PQFP100 Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 256K X 36 ZBT SRAM, 5 ns, PBGA119 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K X 36 ZBT SRAM, 4.2 ns, PBGA119 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 512K X 18 ZBT SRAM, 5 ns, PQFP100 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K X 32 ZBT SRAM, 4.2 ns, PQFP100 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 512K X 18 ZBT SRAM, 4.2 ns, PQFP100 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K × 3256K × 36和管道为512k × 18编号WAIT状态总线的SRAM
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Integrated Silicon Solution, Inc. INTEGRATED SILICON SOLUTION INC
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GS880F18 GS880F36T-11I GS880F36T-14 GS880F36T-12I |
8Mb12K x 18Bit) Synchronous Burst SRAM(8M位(512K x 18位)同步静态RAM(带2位脉冲地址计数器)) 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 256K X 36 CACHE SRAM, 11 ns, PQFP100 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 256K X 36 CACHE SRAM, 14 ns, PQFP100 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 256K X 36 CACHE SRAM, 12 ns, PQFP100 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 512K X 18 CACHE SRAM, 12 ns, PQFP100 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 512K X 18 CACHE SRAM, 11.5 ns, PQFP100 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 512K X 18 CACHE SRAM, 11 ns, PQFP100
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GSI Technology, Inc. Molex, Inc.
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GS880V36BT-250 GS880V18BT-333 GS880V18BT-250 GS880 |
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 256K X 36 CACHE SRAM, 5 ns, PQFP100
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GSI Technology, Inc. http://
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GS88136BGD-300I GS88132BT-200 |
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 256K X 36 CACHE SRAM, 5 ns, PBGA165 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 256K X 32 CACHE SRAM, 6.5 ns, PQFP100
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GSI Technology, Inc.
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EUA6412 |
1M x 8, 3.3V, Sync Burst Pipeline
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德信科技股份有限公司
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GS816272CC-333 GS816272CGC-30I GS816272CC-300 GS81 |
256K x 72 18Mb S/DCD Sync Burst SRAMs 256K X 72 CACHE SRAM, 4.5 ns, PBGA209 256K x 72 18Mb S/DCD Sync Burst SRAMs 256 × 72 35.7的S /双氰胺同步突发静态存储器 256K x 72 18Mb S/DCD Sync Burst SRAMs 256K X 72 CACHE SRAM, 5 ns, PBGA209 256K x 72 18Mb S/DCD Sync Burst SRAMs 256K X 72 CACHE SRAM, 7.5 ns, PBGA209
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GSI Technology, Inc.
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7C33128PFS36A |
3.3V 128K x 32/36 pipeline burst synchronous SRAM
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Alliance Semiconductor
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WEDPZ512K72V-150BI WEDPZ512K72V-150BM WEDPZ512K72V |
512K x 72 Synchronous Pipeline Burst ZBL SRAM
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WEDC[White Electronic Designs Corporation]
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WED2ZL361MV38BI WED2ZL361MV35BC WED2ZL361MV42BC WE |
1Mx36 Synchronous Pipeline Burst NBL SRAM
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WEDC[White Electronic Designs Corporation]
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WEDPZ512K72S-150BC WEDPZ512K72S-150BI WEDPZ512K72S |
512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM
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WEDC[White Electronic Designs Corporation]
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M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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Renesas Electronics Corporation. Renesas Electronics, Corp.
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